1. Technical Field
The present invention relates to a memory device, and more particularly relates to a voltage generating system and a memory device using the same.
2. Description of Related Arts
Complementary metal-oxide semiconductor (CMOS) integrated circuits are susceptible to a parasitic circuit effect called latchup. The result of latchup is the shorting of the supply voltage and the ground of the CMOS circuit, which causes destruction of the chip.
FIG. 1 is a schematic cross-sectional diagram illustrating a portion of a CMOS integrated circuit and the associated parasitic circuit.
Referring to FIG. 1, the CMOS integrated circuit is built on a p-substrate 102 with an n-well 104. The n-well 104 has a well contact 106 coupled to a supply voltage Vint, and the p-substrate 102 has a substrate contact 120 coupled to the ground Vss. A portion of the CMOS integrated circuit includes a PMOS transistor 110 disposed at the n-well 104 and an NMOS transistor 116 disposed at the p-substrate 102. The PMOS transistor 110 includes a p+ region 112 that is coupled to the supply voltage Vint and the NMOS transistor 116 includes an n+ region 118 that is coupled to the ground Vss.
An associated parasitic circuit of the CMOS integrated circuit includes a PNP bipolar junction transistor 124, an NPN bipolar junction transistor 126, a well resistor Rwell and a substrate resistor Rsub. The emitter, base and collector of the PNP transistor 124 are respectively formed by the p+ region 112 of the PMOS transistor 110, the n-well 104 and the p-substrate 102. The emitter, base and collector of the NPN transistor 126 are respectively formed by the n+ region 118 of the NMOS transistor 116, the p-substrate 102, and the n-well 104. The well resistor Rwell couples the base of the PNP transistor 124 to the voltage supply Vint.
The substrate resistor Rsub couples the base of the NPN transistor 126 to the ground Vss.
A situation in which the parasitic circuit of the CMOS integrated circuit enters into the high current latchup state is as follows. Suppose the NPN transistor 126 is turned on. A current flows in the well resistor Rwell, raising the base emitter voltage of the PNP transistor 124 and turning on the PNP transistor 124. Then, a current flows in the substrate resistor Rsub, which in turn raises the base voltage of the NPN transistor 126 and increases the current through the well resistor Rwell, causing a positive feedback condition. The regenerative current effectively creates a low resistive path between the supply voltage Vint and the ground Vss.
Latchup can be induced by a transient substrate bias voltage of the p-substrate 102 that may occur during power-up of the CMOS integrated circuit. Under normal operating condition, the substrate-bias voltage is pumped to a negative voltage by a substrate-bias pump in order to reduce leakage currents and to prevent latchup from being triggered However, under power-up condition, the substrate-bias is not immediately stable and may be coupled to another voltage through parasitic capacitance of the CMOS integrated circuit. Conventionally, a substrate-bias clamp is used to clamp the substrate-bias voltage to ground Vss during power-up. However, the substrate-bias clamp may not be strong enough to hold the substrate-bias voltage at ground level, and prevent triggering of latchup.
Therefore, it is highly desirable that a more effective mechanism to be provided to prevent latchup in a CMOS integrated circuit device.